PassMark MemTest86 - Version History

Version 11.1 (Build 1000) 31/Oct/2024

Fixes/Enhancements
- Improved performance and robustness of using non-default caching policy. This improves UI performance and fixes system halt issues with certain systems.
- Added support for additional caching policies in the main menu and MEMCACHE config file parameter
- Extended SKIPDECODE config file parameter to apply to LPDDR4/LPDDR5 modules
- Updated UEFI libraries to edk2-stable202405 (see https://github.com/tianocore/edk2/releases for details)
- Fixed incorrect test name for test 9 from "ones & zeros" text to "random pattern"
- Fixed multi-core issues on ARM64 chipsets due to unset mask interrupt bit for the ARMv8 performance counter register
- Fixed incorrect slot being identified when ECC errors are detected on Intel Coffee Lake chipsets
- Added address module decoding support for AMD Zen 3 chipsets
- Added workaround when displaying DIMM test results to match the physical slot layout of various consumer Intel Meteor Lake motherboards
- Fixed incorrect channel mode, speeds and timings reported for multi-socket Intel Skylake-SP chipsets
- Fixed incorrect memory timings reported for Intel Emerald Rapids-SP chipsets
- Fixed incorrect reporting of memory timings and channel mode on multi-socket systems
- Fixed incorrect memory speed reported for Intel Sandy Bridge chipsets
- Fixed incorrect memory speed reported for Intel Rocket Lake/Ice Lake/Tiger Lake/Alder Lake chipsets
- Added support for reporting of LPDDR5-specific SPD attributes
- Updated Japanese translations in localizations file (courtesy of Nagisa)

Version 11.0 (Build 1000) 13/Jun/2024

New Features
- Added new configuration file parameter CHECKMEMSPEED for verifying whether the configured memory speed is consistent with one of the SPD profiles or an arbitrary minimum speed specified by the user. If this check fails, an error message is displayed and the memory test will not start. This is useful for confirming that the memory tests are carried out at the maximum speed supported by the RAM.
- Added new configuration file parameter TCPREQUESTLOCATION for specifying the URL request path (and cloud API key) for PassMark Management Console integration
- Added new configuration file parameter TCPGATEWAYIP for setting the default gateway route IP address to allow for connections outside the local network for PassMark Management Console integration
- Added new configuration file parameter SPDREPORTEXTSN for specifying whether to use the module’s extended, 18-digit serial number or standard 8-digit JEDEC serial number in reports. The extended serial number encodes additional manufacture information (including the manufacture ID, date and location) and is more likely to match the serial number printed on the label of the RAM module.
- Added new configuration file parameter DISABLESPD for disabling SPD collection. This is a workaround to prevent throttling of memory speeds, which results in increased test times. This occurs when reading SPD data interferes with the chipset’s Closed-Loop Thermal Throttling (CLTT) mechanism. CLTT is used on a small number of server motherboards to reduce the speed of RAM access when temperatures are too high. But in this case the throttling was seen to be incorrectly activated, due to what we suspect is a BIOS bug.
- Added new configuration file parameter TSODPOLL to enable/disable polling of DIMM temperature sensors (if available). Polling is on by default.
- Preliminary address module decoding support for Intel Meteor Lake/Arrow Lake chipsets. This can help pinpoint the physical location of a memory error.
- Support for collecting memory timings periodically during the test session. When the test completes, the lowest/highest memory speeds are reported. This is to support CPUs that may vary timings in a dynamic fashion.
- Added support for reporting AMD EXPO profiles in DDR5 SPD. EXPO allows for running the RAM at faster than normal speeds without manual overclocking. As always, MemTest86 never changes the BIOS settings. This is just a change to report what profiles are available.
Fixes/Enhancements
- Added TLS (encrypted data) support for PassMark Management Console integration. This is only used when sending test results to the central database for record keeping.
- Added DNS support for PassMark Management Console integration
- Added support for new DDR5 form factors "CDIMM", "CSODIMM" and "CAMM2" for CHIPMAP configuration file parameter. This is to support the new clocked (CUDIMM/CSODIMM) and compact (CAMM2/LPCAMM2) DDR5 form factors supported by newer chipsets (eg. Intel Arrow Lake).
- Increased maximum string length of chip labels to 6 for CHIPMAP configuration file parameter. This is to support longer names used in CUDIMM, CSODIMM and CAMM2 component labels such as “DAR0B0”.
- Fixed bug in address module decoding on Intel Comet Lake chipsets
- Fixed incorrect channel mode detection for the following chipsets:
  - AMD Ryzen
  - Intel Coffee Lake
  - Intel Comet Lake
  - Intel Ice Lake
  - Intel Rocket Lake
  - Intel Tiger Lake
  - Intel Elkhart Lake
- Fixed incorrect memory timings detection for the following chipsets:
  - AMD Ryzen
  - Intel Meteor Lake
  - Intel Arrow Lake
  - Intel Ice Lake-SP
  - Intel Emerald Rapids-SP chipsets
- Fixed incorrect clock speed detection for the following chipsets:
  - Intel Rocket Lake
  - Intel Ice Lake
  - Intel Tiger Lake
  - Intel Alder Lake
  - Intel Meteor Lake
  - Intel Arrow Lake
  - Intel Elkhart Lake
  - Intel Ice Lake-SP
  - Intel Emerald Rapids-SP
- Preliminary support for obtaining memory settings for the following AMD chipsets:
  - AMD K10
  - AMD Bulldozer
  - AMD Piledriver
  - AMD Steamroller
  - AMD Excavator
  - AMD Jaguar
  - AMD Puma
- Preliminary support for multithreading on ARM64, which was previously unavailable due to UEFI BIOS limitations
- Fixed issue with reading DDR5 SPD when the SPD page has not been reset to zero
- Fixed ECC injection option not available on AMD Ryzen Zen 3 chipsets. Note that in general ECC injection is not a feature that is normally accessible by end-users and typically requires a custom BIOS.
- Fixed In-band ECC (IBECC) capability detection on the following chipsets:
  - Intel Tiger Lake
  - Intel Alder Lake
  - Intel Meteor Lake
  - Intel Arrow Lake
  - Intel Elkhart Lake
- Fixed ECC capability detection on Intel Ice Lake-SP and Emerald Rapids-SP chipsets
- Fixed reporting of invalid DIMM temperatures by adding checks for valid Temperature Sensor on DIMM (TSOD) raw data
- Added support for retrieving Intel Meteor Lake and Arrow Lake CPU information
- Updated Chinese and Japanese localization strings (courtesy of Nagisa)
- Updated blacklist to work around specific mainboards/BIOSes with known UEFI multithreading and other issues

Version 10.7 (Build 1000) 8/Feb/2024

Fixes/Enhancements
- Preliminary support for obtaining memory controller settings for Intel Core chipsets. This is for correct reporting of current RAM clock speed & timings. It doesn't impact the actual RAM testing.
  - 2nd gen (Sandy Bridge)
  - 3rd gen (Ivy Bridge)
  - 4th gen (Haswell)
  - 5th gen (Broadwell)
  - 6th gen (Skylake)
  - 7th gen (Kaby lake)
  - 8th gen (Coffee Lake)
  - 9th gen (Coffee Lake Refresh)
  - 10th gen (Comet Lake/Ice Lake)
  - 11th gen (Rocket Lake/Tiger Lake)
  - 12th gen (Alder Lake)
  - 13th gen (Raptor Lake) Core chipsets
- Preliminary support for obtaining memory settings for Intel Core Ultra chipsets:
  - 1st gen (Meteor Lake)
  - 2nd gen (Arrow Lake)
  - Lunar Lake
- Preliminary support for obtaining memory settings for Intel Xeon scalable chipsets:
  - 1st gen (Skylake-SP)
  - 2nd gen (Cascade Lake-SP)
  - 3rd gen (Ice Lake-SP)
  - 4th gen (Sapphire Rapids-SP)
  - 5th gen (Emerald Rapids-SP)
- Preliminary support for obtaining memory settings for Intel Atom X Series (Elkhart Lake) chipsets
- Preliminary ECC support for the following Intel chipsets:
  - 10th gen core (Ice Lake)
  - 1st gen core ultra (Meteor Lake)
  - 5th gen Xeon scalable (Emerald Rapid)
  - Atom X Series (Elkhart Lake)
- Preliminary support for module decoding for Intel 10th gen core (Ice Lake) chipsets
- Added support for reporting various ECC error types (eg. IBECC/Scrub)
- Fixed rounding of DDR5 latency timings
- Fixed offsetted temperatures for AMD 19h family chipsets
- Suppress CPU errors due to UEFI firmware issues once already displayed
- Display "SPD FAIL" block error message when SPDMATCH check fails after test completion
- Updated localization strings (courtesy of Nagisa)
- Updated ImageUSB to v1.5.1006
- Updated blacklist

Version 10.6 (Build 3000) 11/Oct/2023

New Features
- Added support for CFGDEFAULT tag for multi-config files to specify the default configuration
- Added support for CFGTIMEOUT tag for multi-config files to specify the timeout in seconds
Fixes/Enhancements
- Fixed possible divide by zero error when displaying file system info of attached disks
- Fixed system address to UMC decoding for AMD Ryzen chipsets
- Fixed incorrect transfer speed obtained for Alder Lake/Raptor Lake chipsets

Version 10.6 (Build 2000) 29/Aug/2023

New Features
- Extend CHIPMAP configuration parameter to support arbitrary strings up to 4 characters. For backwards compatibility, chip names that are non-negative numbers shall be prepended with "U".
Fixes/Enhancements
- Fixed CPU clock "MHz" cutoff in test screen
- Fixed report summary screen displaying invalid elapsed time and CPU temperatures
- Fixed text cutoff due to long strings for certain languages
- Fixed DIMM temperature text cutoff in test screen for certain languages

Version 10.6 (Build 1000) 17/Aug/2023

New Features
- Added 'SPDREPORTBYELO' and 'SPDREPORTBYTEHI' configuration parameter for specifying the SPD byte range to display in the HTML report
- Implemented workaround for reading DDR5 SPD when SPD write disable (SPDWR) is set for Intel chipsets
- Added DIMM/IC decoding support for AMD Phoenix (19h 74h) chipsets
Fixes/Enhancements
- Added support for chipsets with up to 12 memory controllers
- Fixed hang due to reading non-existent MSR registers for AMD 19h 60-6fh chipsets
- Fixed channel decoding for AMD Ryzen Zen 2/4 chipsets
- Fixed incorrect memory clock reported for Intel Alder Lake/Rocket Lake chipsets
- Fixed incorrect memory clock reported for AMD 19h 60-6fh chipsets
- Fixed incorrect CPU temperature reported for EPYC 7003 series chipsets due to temperature offsets
- Fixed DIMM temperature read failure after reading SPD for certain DDR5 modules
- Added reporting of additional DDR5 SPD attributes
- Fixed hang due memory allocation issues for Intel Skylake/Kaby Lake chipsets
- Added ECC support for additional Intel Skylake-SP chipset variants
- Added workaround for hang when obtaining list of benchmark results
- Perform cache invalidation before start of the RAM benchmark test to fix result inconsistencies
- Fixed text being unaligned when containing full-width characters
- Updated localization strings
- Updated blacklist

Version 10.5 (Build 1000) 19/June/2023

New Features
- Added support for displaying and reporting configured RAM settings for supported chipsets. This includes clock speed, timings, channel mode and voltages.
- Added support for multiple configurations in a single configuration file. If more than 1 configurations are found, the user is prompted to select a configuration
- Added support for displaying and reporting DDR5 XMP 3.0 SPD profiles
Fixes/Enhancements
- Display configured RAM settings in test screen. Previously, static memory parameters from SPD/SMBIOS were displayed which were not necessarily the actual configured parameters.
- Include list of all supported SPD profiles (eg. JEDEC, XMP) in reports
- Changed units from MHz to MT/s when referring to DRAM transfer rate (typically double the clock speed for DDR RAM)
- Reduced the execution time of hammer test by increase minimum segment size per thread from 128MB to 512MB
- Reduced the execution time of hammer test by reducing the maximum number of memory segments to hammer from 64 to 32
- Fixed crash when running the Block Test RAM benchmark
- Added ECC support for Intel Raptor Lake chipsets
- Added DIMM temperature support for Intel Broxton chipsets
- Extended DIMM decoding support for additional Alder Lake and Raptor Lake chipset variants
- Fixed disabling of hyperthreads for CPUs with hybrid cores
- Fixed display of negative CPU temperatures
- Fixed display of negative RAM temperatures
- Fixed inconsistent slot name in DIMM results screen
- Fixed text being truncated in DIMM results screen
- Fixed DIMM error count reporting for 2-slot motherboards
- Fixed TCP connection to management console being refused for certain Apache configurations
- Fixed sending corrupted TCP status XML data to management console
- Fixed error in saving report files due to invalid characters in the file name
- Updated blacklist

Version 10.4 (Build 1000) 20/April/2023

New Features
- Added preliminary support for Ryzen Zen 4 DDR5 chip decoding
- Revised criteria for determining the final result of a memory test
  - PASS – All configured tests were completed without any errors detected
  - FAIL – All configured tests were completed with at least one error was detected or MAXERRCOUNT is exceeded at any point of the test
  - INCOMPLETE PASS – At least one of the configured tests was not completed but no errors were detected
  - INCOMPLETE FAIL –At least one of the configured tests was not completed and at least one error was detected
- Revised criteria for determining the test result of individual modules
  - PASS – All configured tests were completed and no errors were detected on the module without any undecoded errors
  - FAIL – All configured tests were completed with at least one error detected on the module
  - INCOMPLETE PASS – At least one of the configured tests was not completed but no errors were detected on the module without any undecoded errors
  - INCOMPLETE FAIL –At least one of the configured tests was not completed and at least one error was detected on the module
  - UNKNOWN – No errors were detected on the module but there was at least one undecoded error
Fixes/Enhancements
- Added preliminary implementation of ECC injection for Ryzen Zen 4 chipsets
- Fixed module decoding for DDR4 x16 modules
- Display ECC error count in message after completing a test pass
- Fixed incorrect calculation of DDR5 SPD memory bandwidth
- Added additional columns to module result table in HTML report
- Removed "Go back to menu" option from the test menu
- Included '# Tests Completed' in HTML report

Version 10.3 (Build 1000) 24/March/2023

New Features
- Added preliminary support for Ryzen Zen 4 DDR5 module decoding
- Added support for TCP/IP connection to management console
- Added 'INCOMPLETE' result in cases where not all tests complete but no errors are detected
- Added temperatures for all detected DIMMs in HTML/XML report
- Added ECC support for IBECC polling for Tiger Lake Chipsets
- Added additional options for 'SKIPDECODE' config parameter to skip based on DDR type
Fixes/Enhancements
- Added ECC support for Ryzen zen 4 (60h-6fh)
- Fixed Intel Raptor Lake model numbers
- Fixed ECC support for Intel Tiger Lake H and UP3
- Fixed decode UI layout for DDR4 SO-DIMM 1Rx8
- Added ECC channel/slot remap workaround for H12SSL-NT
- Added serial number of failing DIMMs in HTML/XML reports
- Added DIMM S/N in per DIMM error table in HTML report
- Include error count for all DIMMs on test failure in HTML/XML report
- Fixed rank/chip width detection on Intel Tiger Lake chipsets
- Fixed Chip select hash decoding on Ryzen Zen 2/Zen 4 chipsets
- Changed 'EXACTSPDS' configuration parameter to accept an array of values
- Increased main thread wait time if memory error was detected to prevent timeouts
- Added workaround for UEFI firmware being unable to return correct rendered text dimensions
- Fixed freeze on some UEFI firmware when attempting to enable main thread during Multi-Processor init
- Fixed potential boot issues on some MSI Ryzen motherboards
- Fixed bug in parsing DDR5 SDRAM Density Per Die resulting in incorrect module size
- Fix premature main thread timeout in parallel mode due to reporting memory errors
- Fix slot mapping of memory errors for Ryzen AM4 boards
- Fix bug in determining unknown slot errors when there are consecutive errors for the same address
- Fix '# Logical Processors' not appearing properly in XML file
- reduce verbosity of SPD/TSOD SMBus logs

Version 10.2 (Build 1000) 23/Dec/2022

New Features
- Added DIMM and IC decoding for Intel 13th generation Raptor Lake processors
- Added ECC support for Intel Skylake E on HPE platforms
- Added support for retrieving DDR5 SPD on Intel Raptor Lake S
- Added support for retrieving DDR5 SPD on AMD Ryzen 7000 CPUs
- Added 'SKIPDECODE' configuration parameter to skip the decode results screen after completion of tests (Pro/Site Editions)
Fixes/Enhancements
- Modify CHIPMAP config param to include form factor attribute ( e.g. SODIMM, DIMM, etc.)
- Fix bug applying valid CHIPMAP configurations (when # of CHIPMAP entries is < 7)
- Include DIMM rank/chip width in HTML report
- Include DIMM/chip errors in XML file to PXE server
- Fix UI display of SODIMM chip errors
- Fix UI display of DIMM x16 chip errors
- Fix lockup on Mac devices caused by buffer overrun and type overflow in parsing of localization strings
- Fix handling of measuring text width for empty strings causing lockup on Sandy Bridge CPUs
- Fix of SPD channel/slot assignment for Intel E5 v3 chipset
- Fix DIMM result screen to handle boards with unused MC slots ( e.g. Q670EI IM A)
- Fix SODIMM chip ordering in the result screen
- Include unknown DIMM/chip errors in HTML/PXE reports

Version 10.1 (Build 1000) 16/Dec/2022

New Features
- Modified CHIPMAP config file parameter to support multiple DIMM configurations (eg. DDR4|DDR5, x8|x16, 1R|2R, 8GB|16GB)
- Added DIMM and IC decoding for Intel 8th, 9th, 10th and 11th generation processors (Pro/Site editions).
- Added initial support for Raptor Lake, Tremont and Sapphire Rapids chipsets. This includes accurate retrieval and display of processor speed, core status, temperature information and of core group multipliers
Fixes/Enhancements
- Reduced overall image size to allow use of USB flash drives under 1GB
- Fixed ECC channel/slot error details not displaying correctly
- Added “Un-decoded” errors to results screen
- Updated CPU cache speed values to 64bit to prevent overflow errors on faster systems
- Fixed mapping of SMBIOS slot to SPD when there are duplicate serial numbers
- Fixed hyperthread detection when max number of CPU threads are limited (eg. 16 in Free edition)
- Fixed issue allowing multiprocessor cores to exceed max system cores
- Fixed issues when number of CPU cores exceed MemTest86 version's max core limit
- Fixed rounding error with DDR5 clock speed
- Fixed test selection in console only mode

Version 10.0 (Build 1000) 30/Sep/2022

New Features
- Added new experimental memory test as Test 14 [DMA test]. This test exercises the disk controller's DMA hardware to perform memory access, bypassing the CPU. The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA. As this test is experimental, it shall be disabled by default.
- DIMM (Pro edition)/chip-level (Site Edition) error detection on limited number of hardware platforms. This includes mid-test error reporting, graphical UI summary report on test completion and per-DIMM/chip error count table in the HTML report.
  - Added new config file parameter, 'CHIPMAP', to specify the DRAM chip labeling map. By default, DRAM chips are labeled consecutively starting from U0 (eg. U0, U1,…, U15)
Fixes/Enhancements
- Log file name now includes the timestamp
- Added new blacklist flag 'DISABLE_CPUINFO' for disabling CPU info collection
- Fixed 'MAXCPUS' config file parameter not being applied
- Fixed hammer test incorrectly running in single-sided mode in Free version
- Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled
- Fixed detection of MAC address used as unique ID for PXE boot
- Added support for reporting IBECC errors
- Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets
- Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets
- Fixed ECC detection on Intel Ice Lake-SP chipsets
- Added ECC detection support for multi-socket Intel Ice Lake-SP chipsets
- Fixed ECC support for Intel Rocket Lake chipset variant
- Added ECC support for AMD Ryzen Zen 3 50h-5fh chipset
- Fixed ECC support for AMD Ryzen Zen 2 chipsets with 2 memory channels
- Fixed ECC error false positives on Intel Atom C2000 chipsets
- Added support for retrieving Intel Ice Lake-SP CPU info
- Added support for retrieving Intel Ice Lake-SP RAM SPD data
- Added support for retrieving Intel Ice Lake-SP RAM temperature data
- Added SMBus (SPD) support for Intel Alder Lake-P
- Enable SMBus on Intel 801-based chipsets if disabled
- Fixed detection of SPD modules on systems with > 8 SMBus controllers (eg. quad socket systems)
- Fixed bug in mapping SPD module index to SMBIOS slot index
- Fixed detection of SPD slot for systems with soldered and removable DIMMs
- Fixed incorrect calculation of DDR5 transfer bandwidth
- Fixed DDR5 memory type in SMBIOS not being correctly parsed
- Fixed identification of data partition in USB flash drive
- Create 'Benchmark' directory to store RAM benchmark results if it does not already exist
- Updated blacklist

Version 9.4 (Build 1000) 24/Jan/2022

Fixes/Enhancements
- Added new config file parameter, 'MAXCPUS', for setting the maximum number of CPU logical cores used for testing. By default, this value is 256 (Pro Edition) and 16 (Free Version). This parameter can be set to a maximum value of 512.
- Added new config file parameter, 'AUTOPROMPTFAIL', for specifying whether to display the test result and ask for user intervention on test failure, even when AUTOMODE is enabled
- Added new config file naming convention allowing for separate config files depending on memory size: <Memory-size-in-GB>GB-mt86.cfg
- Fixed memory size calculation to use rounding instead of truncation
- Display PASS message box in yellow (instead of green) on test completion if corrected ECC errors were detected
- Display error message if no valid SPD.spd file was found when SPDMATCH=1
- Display error message if no SPD modules were detected when SPDMATCH=1
- Display error message and exit MemTest86 when failing to measure CPU clock speed during startup
- Updated XML message to include CPU info & SMBIOS info sent to PXE server/management console
- Added ECC Support for Intel Tiger Lake H chipset
- Added ECC Support for Intel Rocket Lake chipset
- Added ECC Support for Intel Alder Lake chipset
- Added ECC Support for Intel Ice Lake-SP chipset
- Added support for retrieving CPU info for Intel Elkhart Lake chipset
- Added support for retrieving DIMM temperatures (TSOD) for Intel Alder Lake chipset
- Fixed issue with measuring ARM64 CPU clock speed due to CPU cycle counter (PMCCNTR) being disabled
- Fixed HTML report to display error bit map in text when copying/pasting
- Fixed Linux badram entries in HTML report to be page size aligned (4096 bytes)
- Fixed parsing bug with SPD.spd file when whitespace appears at the end of each line
- Fixed issues with displaying RAM SPD DDR5-specific info
- Fixed support for limited number of command line parameters in Free version
- Fixed bug in overflowing text in SPD info screen
- Fixed REPORTNUMWARN config file parameter not being written when saving config file
- Included Serva PXE server configuration file in Site Edition package
- Updated blacklist with Dell Precision 7760 screen display issues

Version 9.3 (Build 1000) 6/Oct/2021

Fixes/Enhancements
- Support custom test definitions specified by a configuration file. A custom test definition consists of an existing test algorithm, specific test pattern, cache settings, and number of iterations. Custom test definitions are enabled by specifying the TESTCFGFILE parameter (Pro Edition only)
- Fixed incorrectly formatted XML Status/TestResult files sent to PXE/TFTP server (Site Edition only)
- Fixed incorrect reporting of error endianess for 128-bit test
- Fixed bug in displaying/logging ECC error channel/slot number
- Fixed report/log files not being saved correctly for non-standard USB flash drive installs
- Improved responsiveness of pattern string updated on screen
- Display row hammer warning, if applicable, in test completion popup message
- Fixed ECC error reporting on AMD Ryzen chipsets to include channel/slot information
- Fixed ECC error reporting on AMD Ryzen chipsets with 8 memory channels
- Improved robustness of ECC error reporting for Intel Atom C2000 chipsets
- Fixed retrieval of DDR4 SPD bytes on Intel Alder Lake chipsets
- Added support for parsing DDR3 Module Manufacturer’s Specific Data
- Updated blacklist with additional Surface Pro models with display issues

Version 9.2 (Build 2000) 30/Jul/2021

Fixes/Enhancements
- Added large PASS/FAIL block text to top-right corner of HTML report
- Added visual representation of bit error mask to HTML report
- Fixed missing timestamp for ECC errors in HTML report
- Fixed incorrect version string indicating "V9.1" instead of "V9.2"

Version 9.2 (Build 1000) 23/Jul/2021

Fixes/Enhancements
- Preliminary support for retrieving and decoding DDR5 SPD data. This includes support for the new SPD HUB I2C/I3C command set.
- Support for retrieving DIMM temperatures (TSOD) for AMD Ryzen chipsets
- Fixed ECC error polling on Ryzen with multiple controllers
- Fixed ECC detection on AMD Ryzen chipsets (Family 17h Model 31h)
- Improved formatting of the Test Summary screen on test completion
- Moved "RAM Temp" to "Pattern" line to allow longer RAM info display
- Updated blacklist with additional baseboards with known multiprocessing issues
- Refactored code for newer EFI Development Kit (EDK II) release compatibility

Version 9.1 (Build 1000) 21/May/2021

Fixes/Enhancements
- Fixed parsing of SMBIOS memory device structure for compatibility with DDR5 DIMM data
- Fixed non-page aligned addresses for ADDRLIMLO/ADDRLIMHI configuration file parameters
- Fixed hang when running in UEFI Shell caused by improper cleanup of localization strings after an exit from a previous MemTest86 run.
- Added support for retrieving CPU info for Intel Rocket Lake chipsets
- Added support for retrieving CPU info for Intel Tiger Lake chipsets
- Fixed misalignment of text containing full-width characters

Version 9.0 (Build 2000) 24/Feb/2021

Fixes/Enhancements
- Fixed text disappearing in the main menu for certain boards (eg. Thinkpad)
- Fixed artifacts appearing in icons due to improper handling of transparency channel
- Restored option to set # of passes for Free version
- Fixed drawing issues in Upgrade to Pro screen when hovering mouse over sidebar
- Fixed display issues in console mode for certain boards (eg. Supermicro)
- Fixed double temperature offset being applied to certain Ryzen (AMD 17h) chipsets

Version 9.0 (Build 1000) 10/Feb/2021

New Features
- Support UEFI-based ARM systems (arm64/aarch64), including memory test algorithms ported to ARM64 and optimized using hand-written assembly code. Special thanks to Simula eX³ project (ex3.simula.no) for providing high-end ARM64 systems for testing.
- Added BADRAM & badmemorylist formatted strings and instructions in the exported HTML report to mask defective memory addresses (Pro only)
- Revamped RAM SPD screen in the Main Menu with graphical view of all RAM slots
- Added preliminary support for DIMM temperature reporting (when supported by DIMM)
- Added option to change save location of logs/reports to another disk volume (file system)
- Added prompt on various exit options (shutdown, reboot, exit to BIOS) on application exit.
- Added keyboard shortcut (F12) to save screenshot to file within the Main Menu
- Support for saving test results to a byte-packed, binary file for storage-limited systems
- Support for passing configuration parameters via command line arguments
- Added new config file parameter, 'EXACTSPDSIZE', to specify the total capacity of all detected SPD to match before allowing tests to begin
- Added new config file parameter, 'MEMREMMB', for specifying the minimum amount of memory to leave unallocated during testing
- Added new config file parameter, 'MINMEMRANGEMB', for specifying the minimum size of memory ranges that shall be allocated for testing
- Added new config file parameter, 'AUTOREPORTFMT', for specifying report format of auto-saved reports
- Added new config file parameter, 'PMPDISABLE', to disable TFTP uploading of XML messages for Management Console integration
- Added new config file parameter, 'RTCSYNC', to sync real-time clock with PXE server (via a periodically updated 'CurrentTime.txt' served by the PXE server)
- Added new config file parameter, 'VERBOSITY', for specifying the verbosity level of the debug output
- Added new config file parameter, 'TPL', to specify the UEFI task priority level of the MemTest86 application
Fixes/Enhancements
- Support for per-baseboard configuration file via baseboard-prefixed filename (eg. "Surface Pro-mt86.cfg")
- Optimized/removed stale 32-bit code in memory tests
- Improved test coverage by alternating between ascending/descending assignment order of CPU cores between passes when running in parallel mode
- Track CPU core/thread ID of detected memory errors, and include the list of CPUs in error in test summary/report
- Added tracking and reporting of min/max/average CPU + DIMM temperatures (when supported by DIMM)
- Added SMBIOS memory device info to reports
- Modified DRAM address ECC error reporting from (Column,Row,Rank,Bank) -> (Channel,Slot,Rank,Bank,Row,Column)
- Added serial number of DIMM module experiencing ECC errors in report (supported chipsets only)
- Added channel/slot information of detected SPDs in report (supported chipsets only)
- Fixed 100% CPU usage when waiting for input in main menu
- Improved UI drawing performance for better responsiveness
- Generate beeps of Piezo Speaker on test end (if available)
- Changed to large, coloured PASS/FAIL message box on test end
- Changed to large, coloured FAIL message box on failed pre-test SPD checks
- Fixed Test 12 errors in HTML report being truncated
- Updated blacklist to work around new UEFI bugs Apple added to their UEFI firmware
- Updated blacklist to work around Microsoft/Huawei laptops with display issues related to screen resolution
- Fixed crash on VirtualBox due to reading of non-existent MSRs
- Include system information details in TestResult XML messages to PXE Server (Site Edition)
- Display error when there is a TFTP transfer error when sending Status XML messages to PXE server (Site Edition)
- Fixed escaping of chars to XML entities when generating messages to PXE Server (Site Edition)
- Output additional lines to console during MemTest86 boot
- Fixed detection of uncorrected ECC errors for AMD Ryzen chipsets
- Fixed ECC detection for > 2 channels for AMD Ryzen chipsets
- Fixed ECC support for multiple CPU dies for AMD Ryzen chipsets
- Fixed ECC error detection on AMD Ryzen chipsets with multiple CPUs
- Added preliminary support for AMD Ryzen ECC reporting via error count registers when PFEH is enabled
- Fixed ECC detection for Intel chipsets that use error count registers
- Added ECC support for different Intel Coffee Lake chipset variants
- Added disabling of SMI for Intel Kaby Lake chipsets to allow ECC errors to be detected
- Added ECC support for Intel Comet Lake chipsets
- Added preliminary support for decoding of system address to socket/channel/rank/bank/row/column address on Broadwell-DE. This information is logged in the log file.
- Fixed incorrect reporting of ECC capabilities for chipsets with multiple IMCs
- Added support for retrieving CPU info for Intel Gemini Lake chipsets
- Added preliminary support for retrieving CPU info for Intel Ice Lake chipsets
- Fixed potential unstable behaviour when increasing the target multiplier for Intel Silvermont chipsets
- Fixed enabling turbo mode on Intel Silvermont chipsets
- Updated temperature offsets for AMD Ryzen chipsets
- Added preliminary support for reading AMD Ryzen 5000 (Family 19h) chipset temperatures
- Updated EDK2 library to edk2-stable202008
- Fixed memory leak when exiting program
- Revised Portuguese translations
- Updated unifont.bin file with higher weight Russian glyphs
- Removed PassMark contact information from reports

Version 8.4 8/May/2020

Fixes/Enhancements
- Added new config file parameter 'CHECKMEMSPDSIZE' for checking consistency of total memory capacity of detected SPDs against system memory size
- Added new config file parameter 'SPDMATCH'. If enabled, will perform a comparison of the values contained in SPD.spd file with the actual SPD data obtained
- Memory is now reserved at the beginning and released at the end of the test session to reduce frequency of memory allocations/release and improve UI responsiveness
- Added fallback setting to best screen resolution candidate if current screen resolution is outside supported range
- Increased maximum supported screen height from 1080 to 1200
- Added tftp.remap file for fixing backslash/forward slash issues with uploading XML files when running TFTP server on Linux machines
- Added warning message when failing to inject ECC errors for Ryzen chipsets (due to being disabled in production)
- Added disabling of DRAM periodic and redirect scrub when performing ECC injection on Ryzen chipsets
- Added specific Mac Pro models to black list to workaround display and multiprocessing issues
- Added preliminary ECC support for Ryzen Zen 2
- Added preliminary support for retrieving CPU info for Intel Comet Lake chipsets
- Updated Russian translations (courtesy of Victor Lutz)

Version 8.3 22/Nov/2019

Fixes/Enhancements
- Added AUTOREPORT configuration file parameter to enable/disable automatic saving of test results HTML report when AUTOMODE is enabled
- Added TFTPSTATUSSECS configuration file parameter to set the period to send status XML updates to TFTP server (for management console)
- Modified behaviour for detection of duplicate errors. Errors with the same address (and bits) but occur in different tests are no longer considered to be duplicate.
- Fixed hang when CPU does not support SSE4.1 instructions when running Test 12
- Fixed MINSPDS and EXACTSPDS configuration file parameters being incorrectly set when saving current configuration settings to file
- Fixed escaping of characters in XML messages to TFTP server (for management console)
- Fixed invalid XML tag in XML messages to TFTP server (for management console)
- Report is now automatically saved before the end of test prompt when AUTOMODE=2 is set in configuration file
- Fixed incorrect reference to blacklist flag 'TEST12_ONECPU' (correct flag is 'TEST12_SINGLECPU')
- Updated Russian translations (courtesy of Victor Lutz)
- Added better sanity checking for SPD bytes
- Updated JEDEC manufacture list to JEP106AZ (May 2019)
- Fixed channel mapping for Apollo Lake ECC detection
- Fixed ECC detection for certain Intel Skylake-SP chipsets

Version 8.2 3/Jun/2019

Fixes/Enhancements
- Added REPORTPREFIX configuration file parameter to specify the prefix text to use for the report files
- Added TEST12_SINGLECPU flag to blacklist.cfg to force test 12 to run in single CPU mode as a workaround for CPU threads hanging in PARALLEL mode
- Added DISABLE_LANG flag to blacklist.cfg to disable language support and font support, which is known to cause issues on some Dell systems
- Changed the blacklist.cfg RESTRICT_ADDR flag lower address limit from 0x1000 to 0x100000, as some systems experience issues when writing to the BIOS area (up to 0xFFFFF)
- Fixed bug with blacklist.cfg RESTRICT_ADDR flag not setting the lower address limit properly
- Fixed buffer overrun bugs detected by HeapGuard when measuring memory latency
- Fixed fluctuations in memory/cache speed measurements
- Fixed UI issues with System Information screen
- Changed "red" error text to "light red" for better readability
- Fixed CPU temperature readings for several AMD Ryzen chipsets
- Added reporting of Module Manufacturer's Specific Data in DDR4 SPD modules to PXE server for use with Management Console (Site Edition only)
- Fixed timing issues with retrieving SPD data on Skylake-X chipset
- Fixed decoding of DDR4 SPD Post Package Repair (PPR) (Byte 9)
- Fixed decoding of DDR4 SPD Secondary SDRAM Package Type (Byte 10)

Version 8.1 4/Jan/2019

Fixes/Enhancements
- Added version information and total CPU threads to test summary screen
- Increased maximum number of CPU threads to 256
- Added text colour to error messages during testing
- Added Mac Mini 2018 to blacklist which sets the lower address limit to 0x1000 by default
- Fixed bug in detection of hyperthreads when the number of CPU threads exceeds the maximum
- Fixed incorrect JEDEC manufacture names (Bank 10)
- Fixed missing RAM part number / serial number obtained from SMBIOS in HTML report
- Fixed incorrect channel/slot number for ECC errors on Skylake-SP chipsets
- Fixed bug in specifying the number of test passes for Free version

Version 8.0 7/Dec/2018

New Features
- Added ability to save/overwrite current configuration to the mt86.cfg file. This can be done under the 'Settings' screen
- Initial support for KingTiger iMS functionality. In the medium term, this will allow bad RAM addresses to be localized and removed from service, possibly fixing memory errors caused by defective RAM sticks
- Added language support for Polish
- Added new configuration file parameter CONSOLEONLY which forces MemTest86 to run using the console only (ie. no graphics). This allows for systems without graphics support (eg. serial console)
- Added new configuration file parameter SAMESPDPARTNO to check whether the part numbers of all detected SPDs match
- Added new configuration file parameter EXACTSPDS to specify the number of detected SPD modules to match before allowing the tests to begin. This parameter overrides MINSPDS if set.
- Added options to set MINSPDS and EXACTSPDS in the main menu. This can be done by selecting 'View detailed RAM (SPD) info' in the 'System Info' screen
- Improved Test 12 test coverage by alternating between temporal/non-temporal store/load intrinsics. This change allow MemTest86 to detect some previously undetectable RAM errors.
- Added support for memory error triggering and logging for logic analyzers such as Logic Analyzer Keysight U4164A. Before the test is started, the memory address of the structure where errors are logged is displayed on screen to allow for configuration of the logic analyzer. When memory errors are detected, the pattern 0xDEADBEEF and error details are written to a predefined structure. This triggering/logging mechanism is enabled via configuration file parameter TRIGGERONERR.
Fixes/Enhancements
- Removed MemTest86 v4 (BIOS) from boot images. This means that MemTest86 will no longer be dual boot and UEFI is now mandatory to use new versions of MemTest86. On old machines with traditional BIOS, the separate stand alone V4 release will need to be used. This change was made as many users were confused by the dual boot setup, and accidentally booted the old V4 release on new UEFI systems.
- Removed MemTest86 ISO download packages. Users are encouraged to use the USB boot images which allow logs, reports and configuration files to be written to the USB drive. If CD boot is required, please use ISO images from MemTest86 v7 or earlier.
- Consolidated download packages for Windows and Linux/Mac into one zip file
- Increased size of partitions in the boot images to 256MB
- Fixes to allow Memtest86 to be installed permanently in firmware by motherboard vendors
- Fixed system hang when disabling cache on CPU threads
- Memory ranges less than 1MB are no longer reserved for Bit fade test/Hammer test due to possible memory conflict issues
- (Site Edition only) Changed management console report period from 3 min to 1 min. Removed reporting after the completion of every test.
- Added periodic resetting of watchdog timer for iPXE workaround
- Limited the maximum number of passes in the Free version to 4
- Fixed FAIL result in generated HTML report when testing was aborted without any errors.
- Added timestamp to the list of errors in the HTML report
- Fixed misaligned progress bar when running RAM benchmark test
- Updated to UDK2018
- Added CPU/SPD/ECC support for Hygon Dhyana chipsets
- Updated JEDEC RAM manufacture ID list (JEP106AX)
- Added SMBus (SPD) support for Intel Cannon Lake SMBus.
- Added SMBus (SPD) support for unknown Intel SMBuses
- Added ECC detection support for Intel Atom C3000 chipsets
- Added ECC detection and injection support for Intel Coffee Lake chipsets
- Added ECC detection and injection support for AMD Ryzen (10h-1fh) chipsets
- Fixed ECC detection support for Skylake-SP
- Fixed ECC error channel/slot number determination for Skylake-SP
- Fixed bug in reporting of ECC capabilities for Ryzen chipsets
- Fixed Ryzen CPU temperature readings for 26xx/27xx/29xx
- Added workaround for console mode not working for laptops with hi-res screens
- Added iMac14,2 to blacklist which set the lower address limit to 0x1000 by default
- Added ROG STRIX X370-F GAMING (BIOS version 4012) to the blacklist as first BIOS version that doesn't require blacklisting

Version 7.5 (Build 1001) 21/Feb/2018

Fixes/Enhancements
- Fixed AP being reset after every memory segment causing tests to slow down significantly for some systems

Version 7.5 5/Feb/2018

Fixes/Enhancements
- Added check for whether the number of errors exceed a maximum error count. If so, the tests are aborted. This can be configured via the configuration file parameter MAXERRCOUNT. By default the value is 10000
- Added support for Russian language
- Added new configuration file parameter EXITMODE for specifying whether to shutdown or reboot the system on exit
- Added support for reporting to Management Console (https://www.passmark.com/products/bitmgtconsole.htm) via XML messages over TFTP (Site Edition only). The status of MemTest86 is periodically reported to the management console
- Added new configuration file parameter TFTPSERVERIP for specifying a different TFTP server IP address for sending report files and reporting to the management console (Site Edition only)
- Added workaround for retrieving configuration files from TFTP servers that don't support the 'get file size' TFTP command (Site Edition only)
- Added workaround for Serva bug when overwriting a file on the TFTP server (Site Edition only)
- Fixed bug with generated HTML/XML files that require character escaping
- Added workaround when firmware EFI_GET_TIME function fails to retrieve the time correctly. A warning is also written to the log file
- Added new flag DISABLE_CONCTRL to blacklist for console control workarounds for older firmware
- Fixed 'ALL' BIOS versions not being parsed properly in blacklist
- Updated blacklist.cfg file with additional baseboards with known issues
- Added more robust detection of CPU hyperthreads
- Added ECC detection support for Intel Skylake-SP chipsets
- Added ECC detection/injection support for AMD Ryzen chipsets. Note that injection support is typically disabled by AMD, except for some CPUs which are engineering samples.
- Added warning message to log file when ECC injection is locked on Atom C2000 chipsets
- Fixed bug with ECC error reporting on Intel Xeon E3 chipsets
- Fixed CPU temperature not being shown for Intel Apollo Lake, Skylake-X and Broadwell-E chipsets
- Added preliminary support for retrieving CPU info for Intel Cannon Lake/Knights Mill chipsets
- Fixed bug with retrieving the number of boosted P-states in AMD chipsets
- Fixed CPU temperature not being read properly on AMD 15h (model >= 40h) chipsets

Version 7.4 26/July/2017

Fixes/Enhancements
- Added new file blacklist.cfg that contains a list of baseboards that have known MemTest86 boot issues
- Added 'CONSOLEMODE' config file parameter for specifying the mode of the UEFI console. Setting the console mode determines the resolution of the console (with 0 being the minimum supported resolution of 80x25)
- Added 'BITFADESECS' config file parameter for specifying the sleep interval in the Bit Fade test (Test 10)
- Added language support for Catalan
- Updated ImageUSB to version 1.3
- Fixed 128-byte alignment issues in the random library
- Errors detected in Test 12 (128-bit Random Number Sequence Test) are now logged as 128-bit values
- HTML test report now includes if ECC polling was enabled
- Fixed text artifacts appearing in the testing screen due to the text being too long
- Fixed memory size being incorrectly reported due to including non-RAM memory ranges (eg. NVM, MMIO, Reserved)
- Fixed main menu screen being too small due to resolution being set too high
- Added preliminary ECC Injection support for Intel Xeon E5 chipsets
- Added preliminary ECC Injection support for Intel D-1500 chipsets
- Added ECC detection support for different variations of Intel Kaby Lake chipset
- Added support for retrieving AMD Ryzen CPU info, including base and turbo clock speeds
- Improved the performance and robustness of measuring CPU base/turbo speeds for AMD chipsets
- Updated JEDEC RAM manufacturer ID list
- Added reset mechanism for Intel ICH SMBus when timeout occurs while accessing SPD registers
- Fixed DDR4 SPD data not being read for PIIX4 SMBus controllers

Version 7.3 27/Feb/2017

Fixes/Enhancements
- CPU cores that are identified as hyperthreads are now disabled by default, due to minimal performance benefits
- Fixed potential system hang caused by memory alignment issues when allocating 128-bit variables on the stack during the 128-bit random number sequence test (Test 12)
- Improved performance of the 128-bit random number sequence test (Test 12) by using SSE2 comparison intrinsics
- Improved performance of the row hammer test (Test 13) by increasing the default step size to 0x1000000 (16MB) for subsequent passes after the first pass. On the first pass, the default step size is 0x4000000 (64MB)
- Reduced test time of the row hammer test (Test 13) by using only a single offset bit to determine the row address pair, rather than cycle through all possible offset bits.
- Added 'ENABLEHT' config file parameter to enable/disable CPU cores identified as hyperthreads
- Added 'HAMMERSTEP' config file parameter to specify the step size for the next row pair to hammer in the row hammer test (Test 13). Increasing the step size reduces the memory test coverage, but will also decrease the test time. By default, the step size is 0x1000000 (16MB)
- Added several known baseboards to a 'blacklist' of boards that have known issues when running in multiprocessor mode. If a blacklisted baseboard is detected, the Multiprocessor test is skipped during startup and the CPU selection mode is set to single.
- Fixed triggering of ECC error injection on Intel Skylake (Xeon E3 v5) chipset
- Added ECC detection and injection support for Intel KabyLake (Xeon E3 v6 family) chipsets
- Added ECC detection and injection support for Apollo Lake SoC (Atom E3900 Series) chipsets
- Added support for retrieving RAM SPD data on Intel Skylake-E chipsets
- Fixed issue with the test elapsed time having strange values when running in round robin or sequential CPU mode due to the timestamp counter not being synchronized on the CPU cores

Version 7.2 13/Dec/2016

Fixes/Enhancements
- Language support for Italian
- Added ECC detection support for Broadwell-H chipsets
- Added ECC injection support for Broadwell-H chipsets
- Added ECC detection support for AMD Merlin Falcon
- Added fix for certain Intel Xeon E5 platforms that are unable to access the ECC and SMBus registers
- TSOD polling is now temporarily disabled on Intel E5 v3 platforms when reading SPD bytes. Previously, this caused invalid bytes to appear in the SPD data.
- Added sanity check for invalid characters in the SPD part number string
- Updated JEDEC ID manufacture names
- Fixed crash when the number of processors is greater than the max supported (120)
- Added SMBIOS system, baseboard and BIOS info to MemTest86 reports
- Reduced the number of decimal points when displaying memory/cache speeds
- Added workaround for certain UEFI firmware when setting console resolution
- Report file name is now prepended with the baseboard serial number when running MemTest86 Site Edition in order to distinguish from reports from other machines
- Added "Mac-F42C88C8" to a blacklist of known unsupported baseboard/EFI firmwares. When a blacklisted baseboard/EFI firmware is detected, a warning message is displayed.
- Updated to latest UDK + compiler tools
- Various system info related updates/fixes (CPU)

Version 7.1 5/Aug/2016

Fixes/Enhancements
- Fixed a bug in measuring CPU clock speed using HPET which could skew the clock speed results to unreasonable values. This may have caused issues during startup including extremely long loading times
- Added fallback mechanism to use the legacy PIT to measure the clock speed if the measured CPU clock speed using HPET is unreasonable
- Disabled code optimization for Test 12 due to reported freeze when running in parallel mode
- Fixed CPU selection mode not being set according to the results of the multiprocessor test during startup
- When switching to the next target CPU in Sequential/Round Robin mode, attempt to reset the target CPU if there was a failed attempt to switch the BSP
- When looking for SMBus devices for RAM SPD retrieval, attempt to look for any disabled SMBus devices to enable before enumerating the PCI bus
- Fixed cursor appearing for some systems during testing

Version 7.0 20/July/2016

New Features
- Row Hammer Test (Test 13) now uses double-sided hammering and random data patterns in an attempt to expose more RAM modules susceptible to disturbance errors.
- PXE network boot is now fully supported (MemTest86 Site Edition only) to support scalable, diskless deployment to PXE-enabled clients. Like the Pro version, the configuration file (acquired from the PXE server via TFTP) can be used for customization and configuration of MemTest86 memory tests. Report files can also be uploaded to the server. Logging, however, is unavailable.
- Memory tests are run in Parallel CPU mode by default, if supported by the UEFI firmware. Running in parallel mode significantly decreases the test time as compared to running in single CPU mode and should also help to detect more errors faster. This was made possible after developing a work around for UEFI BIOS bug that prevented multi-threading on some machines.
- Added 'HAMMERPAT' config file parameter to specify the data pattern to use for the row hammer test. By default, random data patterns are used.
- Added 'HAMMERMODE' config file parameter to specify whether to use single or double sided hammering. By default, double-sided hammering is used.
- Added 'CPULIST' config file parameter to specify a subset of available CPUs to enable for the memory tests.
- Added 'DISABLEMP' config file parameter to disable multiprocessor support in MemTest86. This can be used as a workaround for certain UEFI firmwares that have issues running MemTest86 in multi-CPU modes.
- Added 'BGCOLOR' config file parameter to specify the background colour to use
- Added Portuguese translations
- Added Czech translations
Fixes/Enhancements
- Added ECC support for different revisions of Intel Skylake memory controllers
- Fixed ECC detection on Intel Broadwell-H chipsets
- Changed how ECC errors are detected on Broadwell chipsets
- Changed how ECC errors are detected on Atom C2000 chipset
- Fixed incorrect channel/slot number being reported for ECC errors on E5 chipsets
- Added SMBUS (SPD) support for Intel Broxton
- Added SMBUS (SPD) support for Intel Airmont
- Added SMBUS (SPD) support for Intel Sunrise Point-LP
- Reduced the number of iterations for the Modulo 20 Test (Test 9) to decrease the test time
- Reduced the number of addresses to be hammered for the Row hammer Test (Test 13) to decrease the test time
- When no tests are completed, the test report now displays "N/A" as oppose to "PASS"
- The High Precision Event Timer (HPET) is now used to measure the clock speed, if available. Otherwise, the older Programmable Interval Timer (PIT) is used.
- The clock speed displayed in the RAM info is now the effective clock speed as opposed to the actual clock speed. The effective clock speed is twice the actual clock speed for DDR RAM.
- Speeds greater than 10000MB/s are converted to GB/s when displaying memory/cache speeds in the test screen
- Memory sizes greater than 10240MB are now displayed in GB
- Console is no longer forced to 80 x 25 if the current mode has a higher resolution
- Fixed issue with certain UEFI firmware when switching from console to graphics mode
- Fixed RAM benchmark chart title string overflow
- Various system info related updates/fixes (CPU)

Version 6.3.0 27/Jan/2016

New Features
- New configuration file parameters MINSPDS, SPDMANUF and SPDPARTNO to specify the values that the RAM SPD must match before allowing the tests to start. This may be useful for RAM manufacturers that need to verify that the SPD data has been programmed correctly.
- New configuration file parameter SKIPSPLASH to skip the 10 second splashscreen and proceed directly to the main menu
- New mode for the configuration file parameter AUTOMODE to specify that MemTest86 shall run the tests immediately (skipping the splashscreen and main menu) but prompt the user to save the results after test completion
- New configuration file parameters ADDR2SLBITS and ADDR2CSBITS to specify the bit positions of a memory address to exclusive-or (XOR) to determine which DIMM slot/chip select (0 or 1) corresponds to the failure address
Fixes/Enhancements
- Added ECC detection support for Broadwell-H chipset
- Added ECC detection support for Broadwell-DE chipset
- Added ECC detection support for AMD Bald Eagle (2nd generation Embedded R-series)
- Added ECC injection support for AMD Steppe Eagle/Bald Eagle
- Added SMBus (SPD) support for Broadwell-DE
- Fixed decoding of JEDEC manufacture names from the SPD
- DDR3 XMP rev1.3 SPD decoding is now supported
- Fixed retrieval of DDR4 SPD bytes for Intel ICH SMBUS
- Added workaround for buggy firmware when calls to EFI MPServices fail
- Fixed MemTest86 freezing on network boot
- Fixed bug with wrong details being displayed for detected memory warnings in the report file
- Fixed bug with CPU type detection for older CPUs
- Fixed benchmark chart not being displayed after running a RAM benchmark test when there is a failure in saving results to disk
- Report file now includes the RAM serial number, if available
- Various system info related updates/fixes (CPU)

Version 6.2.0 8/Sept/2015

New Features
- Due to the high number of failures reported for the Hammer Test (Test 13), the algorithm was revised to perform 2 potential passes:
  1. Row pairs are hammered at the maximum hammer rate. (ie. no delays between each row pair hammer)
  2. Row pairs are hammered at a lower hammer rate (200K per 64ms, as determined by memory vendors as the worst case scenario)
- The details of the errors that were detected in the first pass of the Hammer Test but not during the second pass can be displayed in the report by specifying the configuration file parameter 'REPORTNUMWARN'. This parameter represents the maximum number of warnings to display in the report file.
- New configuration file parameter 'AUTOMODE' for full automation. Enabling this parameter shall result in the following:
  - Splash screen is skipped and the tests are started immediately
  - When the tests are completed, the report is saved to disk automatically
  - System is rebooted
Fixes/Enhancements
- Shortened the test time for Hammer Test (Test 13) by reducing the total number of hammers per row address pair
- Fixed issue with the main menu not displaying for certain EFI firmware. Due to the fact that many EFI firmwares require the use of the obsolete ConsoleControl protocol to switch between graphics/console mode, the graphics/console mode workaround is now enabled by default.
- Fixed bug with details of empty RAM slots being displayed when using SMBIOS memory device information
- Added Intel Skylake ECC support
- Updated Jedec manufacturer ID list for displaying the vendor name from RAM SPD. Fixed Jedec manufacturer ID lookup function to support > 7 continuation codes.
- Fixed AMD Hudson-2/Hudson-3 SMBus support to include various hardware revisions
- Various system info related updates/fixes (SPD, CPU)

Version 6.1.0 5/June/2015

New Features
- New config file parameter REPORTNUMERRS for specifying the maximum number of errors to include in the report
- Language support for Spanish
- RAM details obtained from SMBIOS are now displayed if SPD information cannot be accessed
Fixes/Enhancements
- Added ECC detection support for Intel Atom C2000 SoC chipset
- Added ECC injection support for Intel Atom C2000 SoC chipset
- Added ECC injection support for Intel Xeon E3 (Sandy Bridge/Ivy Bridge) chipset (untested)
- Added SMBus (SPD) support for Intel 5100 chipset
- Added SMBus (SPD) support for Intel Wildcat Point chipset
- Added SMBus (SPD) support for Intel Sunrise Point chipset
- Improved speed of retrieving SPD data
- Fixed potential issue with retrieving DDR4 SPD due to the bank address not being restored back to its original value
- Fixed decoding of ECC support in DDR2 SPD
- Added support for more precise timings supported by DDR3 rev 1.1 and later
- Fixed bug with retrieving SPD details for a large number of RAM modules (ie. > 16)
- Fixed the progress indicator for Test 13 (Row hammer test) to be more linear
- Reduced the test time for Test 13 (Row hammer test)
- Fixed the displayed error details when ECC errors are detected
- Fixed freeze while initializing the screen for some firmwares due to an unsupported driver protocol
- Added workaround for incorrect text length/height returned by the UEFI firmware
- Added checks for the number of cores exceeding the maximum supported in MemTest86
- Synchronized cache enabling/disabling across all CPUs
- Migrated CPU cache info code from PerformanceTest/BurnIn Test. The displayed cache info should now be more consistent with what is displayed in BurnIn Test/Performance Test.
- Fixed Enabling/Disabling of features in the Sys Info screen to be less confusing
- Fixed CPU Selection screen to truncate the list of available processors when more than 16 are available
- Various system info related updates/fixes (CPU)

Version 6.0.0 13/Feb/2015

New Features
- Support for DDR4 RAM (and associated hardware), including retrieval and reporting of DDR4-specific SPD details. This includes DDR4 RAM that support Intel XMP 2.0 DDR4 RAM timings.
- New RAM benchmarking feature allowing results to be graphed and saved to disk. Previous results can be graphed on the same chart for comparison.
- New "Hammer Test" for detecting disturbance errors caused by charge leakage when repeatedly accessing addresses in the same memory bank but different rows in a short period of time.
- Language support for French/German/Japanese/Chinese. All text are displayed in the selected language, including generated reports.
Fixes/Enhancements
- Added Haswell-E CPU (DDR4) ECC support
- Added Xeon E5 v3 ECC support
- Added Ivy Bridge CPU (non-Xeon) ECC support
- Added AMD Steppe Eagle CPU ECC support
- Added Intel Atom E3800 SoC ECC support
- Fixed ECC detection for Ivy Bridge-EX / Haswell-EX chipsets that have a 2nd memory controller
- Fixed Intel 5400 ECC registers not being reset after starting test
- Fixed ECC errors immediately being reported after starting test (Ivy Bridge-E)
- Added support for ECC injection for Intel Xeon E3 v3 (untested)
- Fixed handling of Intel ICH SMBUS built-in hardware semaphore to prevent SMBus device contention
- Fixed possible crash when DDR3 module type value in the RAM SPD info is invalid
- Fixed DDR4 SPD clock speed rounding errors in the RAM SPD info
- Fixed DDR3 SPD Register manufacturer/type in the RAM SPD info not appearing correctly
- CPU speed measurement is now more robust by taking multiple samples
- Fixed Intel turbo clock speed calculation
- Fixed detection of Intel turbo support for Xeon chipsets
- Increased maximum # of supported CPUs to 72
- Increased maximum # of supported RAM modules to 64
- Increased the number of supported memory controllers to 8
- New config file parameter 'ECCINJECT' for specifying whether to enable/disable ECC injection
- New config file parameter 'MEMCACHE' for specifying whether to enable/disable memory caching
- New config file parameter 'PASS1FULL' for specifying whether the first pass should run the full iteration or reduced iteration
- New config file parameter 'ADDR2CHBITS' to specify the address bits to XOR to determine the memory channel
- New config file parameter 'LANG' for specifying language to use on startup
- Console resolution is now forced to 80 x 25
- Graphics resolution is now set to a minimum of 1024 x 768
- Updated ImageUSB to v1.1.1015 which includes an option to zero the USB drive. This is useful to recover Flash drive capacity
- Running memory tests in parallel mode is now more robust for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
- Fixed detection of the number of enabled processors for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
- Fixed test status screen not being displayed correctly for consoles with small/large screen widths
- In the RAM SPD menu screen, PGUP/PGDN can be used to navigate between pages of RAM modules
- For specific cases where files under EFI\BOOT cannot be accessed (eg. grub2), log/report files shall be written to the root directory
- During MemTest86 boot-up, the system memory map is now written to log file for debugging purposes
- Various optimizations of the size of the MemTest86 binary
- Forced a memory address limit of 32-bits when running under 32-bit UEFI, fixing an 32bbit overflow bug on some systems
- Memory ranges to be tested are now allocated at the beginning of each test (due to the possibility that the memory map changes in the middle of testing)
- Reduced the number of log messages written when waiting for other processors to finish when running in parallel mode
- When allocating memory for Bit Fade Test, leave 1MB of free memory available (to prevent firmware drivers from running out of memory)
- Fixed potential crash or other unexpected behaviour due to memory issues with random functions
- Reports are now saved using UTF16 encoding to support Unicode characters
- Changed memory allocation behaviour by only pre-allocating memory segments >= 16MB to prevent memory starvation
- MemTest86 is code signed by Microsoft. Allowing support for secure boot (like V5). But V6 now uses a extended validation (EV) certificate.

Version 5.1.0 16/May/2014

- Fixed ECC error detection for Ivy Bridge-E chipsets
- Fixed rounding of memory SPD timings
- On 32-bit systems, systems with upper address limit > 32-bits freezing during testing is now fixed
- Locking memory for testing is now more robust
- Added SPD support for VT8237S, Intel X79, Intel NM10 Chipsets
- Fixed incorrect decoding of # of banks in DDR2 FB SPD causing the memory stick size to be reported incorrectly
- Increased the number of supported memory modules from 16 to 32
- Increased the maximum number of SMBus controllers to 8
- DDR3 revision 1.3 SPD decoding now supported
- Fixed SMBUS CLK issues when retrieving SPD details for Intel chipsets
- CPU spec updates, AMD Kaveri + Intel Haswell refresh
- Xeon (Ivy Bridge and later) non-Turbo CPU speeds now recorded.
- Minor temperature reporting changes for AMD Family 15h, Models 0h-0Fh and 30h-3Fh (e.g. A10-7850K)
- Fixed "Pass" progress bar so that it shows 100% on completion of one pass
- A notification text is now displayed when ECC errors are injected
- Improved notificaion text displayed when ECC errors are detected
- Updated MemTest86 BIOS version to 4.3.7

Version 5.0 release for UEFI 3/Dec/2013

- Completely re-written to work under UEFI.
- Native 64-bit support
- No longer requires the use of the PAE workaround to access more than 4GB of memory. (PAE = Physical Address Extension)
- Mouse support, where supported by the underlying UEFI system. On older systems a keyboard is still required.
- Improved USB keyboard support. The keyboard now works on systems that fail to emulate IO Port 64/60 correctly. So Mac USB keyboards are now supported.
- Improved multi-threading support, where supported by the underlying UEFI system.
- Dual boot with Memtest version 4 for supporting older systems without UEFI. So with a single USB or CD drive both UEFI systems and BIOS systems can be supported.
- Reporting of detailed RAM SPD information. Timings, clock speeds, vendor names and much more.
- Support to writing to the USB drive that Memtest is running from for logging and report generation. In all prior MemTest releases there was no disk support.
- Use of GPT. (GUID Partition Table)
- ECC RAM support (limited hardware support, ongoing development)
  - Detection of ECC support in both the RAM and memory controller
  - Polling for ECC errors
  - Injection of ECC errors for test purposes. (limited hardware only)
- Option to disable CPU caching for all tests
- Support for reading parameters from a configuration file to allow settings to be predefined without the need for keyboard input. This can help with automation.
- Support for Secure Boot
- Speed improvements of between 10% and 30%+. Especially for tests, #5, #8 & #9. This is the result more moving to native 64bit code, removing the PAE paging hack, switching compilers and using faster random number generation algorithms.
- Addition of 2 new memory tests to take advantage of 64bit data and SIMD instructions.

Version 4.3.7 13/May/2014

- Fixed freeze (particularly for older machines) caused by incorrect handling of RSDP revision 0 in the multiprocessor detection code.
- Added menu option for enabling serial console mode.

Version 4.3.6 14/Nov/2013

- Fixed crash (particularly for AMD machines) that is seemingly resolved by adding CPU synchronication barriers before and after performing the memory speed test
- Fixed an error in setting the barrier structure's base address, preventing a possible crash or freeze of the system.
- Added a check to perform a spin lock only when more than 1 CPUs are detected

Version 4.3.5 24/Oct/2013

- Fixed potential error due to barrier structure located at fixed memory location
- Fixed block move test freeze on higher memory addresses

Version 4.3.4 2/Oct/2013

- Fixed incorrect progress calculation for test 0
- Fixed incorrect memory size due to bug with memory map when the e820 entry size member is 0
- Fixed incorrect number of CPU's found due to duplicate entries in the MADT
- Changed the method used to search for processors to searching the APIC MADT first, then search the MP spec table (as opposed to vice versa). The MP spec table has largely been deprecated.

Version 4.3.3 11/Sept/2013

- Fixed incorrect progress calculation for test 4
- Fixed potential false positives in parallel mode caused by overlapped/unaligned memory chunk allocations per CPU
- Fixed program freeze when selecting test 0 or 1 when running in non-parallel mode

Version 4.3.2 22/Aug/2013

- Memory bandwidth is now measured for one CPU (as opposed to being a total for all CPUs & Cores). This will lower the reported bandwidth for multi-core machines. But we think it makes more sense this way.
- Fixed crash when attempting to boot on older single core machines with hyperthreading. Only effects old machines, from around the early Pentium 4 era, that didn't have a MP (Multi-Processor) Spec table defined but did have both a MADT (Multiple APIC Description Table) defined and hyperthreading enabled.
- Restored the "Start only one CPU" boot option. This option should not be required in normal use, but might be useful for debugging purposes.
- Updates to the included help file

Version 4.3.1 8/Aug/2013

- Fixed bug with Test 6 (Block Move Test) not testing the end of a memory segment correctly. This bug could have resulted in false errors being reported in Test #6. The false errors were rare in normal use, but could be provoked more easily by running the tests out of order. e.g. running Test #1, then Test #6.
- Removed unnecessary boot options in menu

Version 4.3.0 10/Jul/2013

- Changed default CPU selection mode to round robin. Running all CPUs at once has been shown to cause false positives on a number of systems.
- Fixed a bug that could cause the program to go into a tight loop that could not be escaped when setting certain memory ranges to test.
- Fixed a bug displaying the memory location of individual errors. The values after the decimal point in the MB readout were incorrect.
- Fixed a bug in configuring upper and lower memory limits, previously lower limits equal or grater than 2gb would not work, as well as some other more obsucre configurations.
- Added a misc option to display the systems memory map.
- Fixed a bug that would cause the number of passes to not correctly reset after changing the selected tests.
- Added missing source code to some of the download packages.
- Fixed a bug in test 8 causing a single error to cascade into multiple errors.
- Fixed a bug causing the average error bits to be incorrect once the errors had maxed out at 65k
- Fixeda bug preventing test 10 to be selected as a single test to run.
- Fixed bug displaying individual test error counts.
- Fixed bug making overall errors 10x what they should be.

Version 4.2.0 18/Mar/2013

- Fixed issues with USB keyboards. The USB keyboard functionality is memory mapped into a portion of low memory on some (maybe many) machines, typing on a USB keyboard changes some values in RAM as the key presses are stored in memory as you type. This can cause the keyboard to become unresponsive during testing or input from the keyboard to generate errors in the tests.
- Fixed crash when configuring memory ranges. Changing the meory range during the first test, or changing the memory range multiple times during later tests could cause the current test number to become negative, triggering a crash.
- Fixed highest error address not reporting correctly on error.
- Fixed error counters overflowing and reseting to 0 after too many errors.
- Fixed max contiguous error reporting.
- Cleaned up some UI text.
- The Windows USB package now includes ImageUSB to make creating Memtest86 USB drives easier.

Version 4.1.0 Jan/2013

- Added a new boot trace option that single steps through the testing process and displays messages and data that is valuable in diagnosing problems with test execution. A large number of trace points have been added in key portions of the code (in particular SMP startup routines) to provide visibility of obscure failures. This feature will allow non-technical users to provide troubleshooting data for better test stability.
- Added a new One Pass feature. This feature runs the complete test once and then exits, but only if there were no errors. This provides a convenient method for unattended testing. One Pass may be enabled via a boot option or via an on-line command.
- Images for CD, USB key and Floppy disks now use Syslinux for booting and include a variety of standard options and two previous versions of MemTest86. The new boot time options may be specified at the boot prompt.
- A feature has been added to allow customization of the list of tests to be run. The test list may be specified via a boot option or via an on-line command.
- A feature has been added to restrict specific CPUs that are to be used for testing. The maximum number of CPUs may be specified or a 32 bit CPU mask may be specified. These are enabled with boot options.
- A number of problem with use of on-line commands when testing with more than one CPU have been fixed.
- A selection of boot time parameters are were added. These options enable boot tracing, the One Pass feature, limit the maximum number of CPUs to use, specify a CPU mask to select CPUs to be used and setup serial console parameters.
- Improved and extended CPU identification routines. Newer CPUID based method is now used to determine cache sizes for Intel CPUs for better accuracy and support-ability.
- Routines for calculating cache and memory speeds have been reworked for better accuracy. An overflow problem has been fixed that resulted in no memory speed being reported for CPUs with large L3 caches.
- Fixed some errors in the crash reporting routines.
- Misc minor fixes and code cleanup.

Version 4.0 28/Mar/2011

- Support for testing with multiple CPUs. All tests except for #11 (Bit Fade) have been multi-threaded. A maximum of 16 CPUs will be used for testing.
- CPU detection has been completely re-written to use the brand ID string rather than the cumbersome, difficult to maintain and often out of date CPUID family information. All new processors will now be correctly identified without requiring code support.
- All code related to controller identification, PCI and DMI has been removed. This may be a controversial decision and was not made lightly. The following are justifications for the decision:
  1. Controller identification has nothing to do with actual testing of memory, the core purpose of MemTest86.
  2. This code needed to be updated with every new chipset. With the ever growing number of chip-sets it is not possible to keep up with the changes. The result is that new chipsets were more often than not reported in-correctly. In the authors opinion incorrect information is worse than no information.
  3. Probing for chipset information carries the risk of making the program crash.
  4. The amount of code involved with controller identification was quite large, making support more difficult.
  Removing this code also had the unfortunate effect of removing reporting of correctable ECC errors. The code to support ECC was hopelessly intertwined the controller identification code. A fresh, streamlined implementation of ECC reporting is planned for a future release.
- A surprising number of conditions existed that potentially cause problems when testing more than 4 GB of memory. Most if not all of these conditions have been identified and corrected.
- A number of cases were corrected where not all of memory was being tested. For most tests the last word of each test block was not tested. In addition an error in the paging code was fixed that omitted from testing the last 256 bytes of each block above 2 GB.
- The information display has been simplified and a number of details that were not relevant to testing were removed.
- Memory speed measurement has been parallelized for more accurate reporting.
- This is a major re-write of the MemTest86 with a large number of minor bug-fixes and substantial cleanup and re-organization of the code.

Version 3.5 3/Jan/2009

- Limited support for execution with multiple CPUs. CPUs are selected round-robin or sequential for each test.
- Support for detection of additional chipsets. (from MemTest86+ v2.11).
- Additions and corrections for CPU detection including reporting of L3 cache.
- Reworked information display for better readability and new information.
- Abbreviated iterations for first pass.
- Enhancements to memory sizing.
- Misc bug fixes.

Version 3.4 (2/Aug/2007)

- Added an error summary display.
- Added support for additional chipsets. (from MemTest86+ v1.70).
- Additions and corrections for CPU detection.
- Support for memory module information reporting.
- Misc bug fixes.

Version 3.3 (12/Jan/2007)

- Added support for additional chipsets. (from MemTest86+ v1.60)
- Changed Modulo 20 test (#8) to use a more effective random pattern rather than simple ones and zeros.
- Fixed a bug that prevented testing of low memory.
- Added an advanced menu option to display SPD info (only for selected chipsets).
- Updated CPU detection for new CPUs and corrected some bugs.
- Reworked online command text for better clarity.
- Added a fix to correct a Badram pattern bug.

Version 3.2 (11/Nov/2004)

- Added two new, highly effective tests that use random number patterns (tests 4 and 6)
- Reworked the online commands:
  - Changed wording for better clarity
  - Dropped Cache Mode menu
- Updated CPU detection for newer AMD, Intel and Cyrix CPUs
- Reworked test sequence:
  - Dropped ineffective non cached tests (Numbers 7-11)
  - Changed cache mode to "cached" for test 2
  - Fixed a bug that did not allow some tests to be skipped
  - Added bailout for Bit fade test
- Error reports are highlighted in red to provide a more vivid error indication
- Added support for a large number of additional chipsets (from MemTest86+ v1.30)
- Added an advanced setup feature that with new chipset allows memory timings to be altered from inside MemTest86. (from MemTest86+ v1.30)
- Misc bug-fixes and code cleanup.

Version 3.1a (11/Mar/2004)

- Added processor detection for newer AMD processors
- Added new "Bit Fade" extended test
- Fixed a compile time bug with gcc version 3.x.
- E7500 memory controller ECC support
- Added support for 16bit ECC syndromes
- Option to keep the serial port baud rate of the boot loader

Version 3.0 (22/May/2002) - Provided by Eric Biederman

- Testing of more than 2gb of memory is at last fixed (tested with 6Gb)
- The infrastructure is to poll ecc error reporting chipset registers, and the support has been done for some chipsets.
- Uses dynamic relocation information records to make itself PIC instead of requiring 2 copies of MemTest86 in the binary.
- The serial console code does not do redundant writes to the serial port. Very little slow down at 9600 baud.
- You can press ^l or just l to get a screen refresh, when you are connecting and unconnecting a serial cable.
- Net-booting is working again
- Linux-BIOS support (To get the memory size)
- Many bug-fixes and code cleanup

Version 2.9 (29/Feb/2002)

- The memory sizing code has been completely rewritten. By default MemTest86 gets a memory map from the BIOS that is now used to find available memory. A new online configuration option provides three choices for how memory will be sized, including the old "probe" method. The default mode generally will not test all of memory, but should be more stable. See the Memory Sizing section for details.
- Testing of more than 2gb of memory should now work. A number of bugs were found and corrected that prevented testing above 2gb. Testing with more than 2gb has been limited and there could be problems with a full 4gb of memory.
- Memory is divided into segments for testing. This allow for frequent progress updates and responsiveness to interactive commands. The memory segment size has been increased from 8 to 32mb. This should improve testing effectiveness but progress reports will be less frequent.
- Minor bug fixes

Version 2.8 (18/Oct/2001)

- Eric Biederman reworked the build process making it far simpler and also to produce a network boot-able ELF image.
- Re-wrote the memory and cache speed detection code. Previously the reported numbers were inaccurate for Intel CPU's and completely wrong for the Athlon and Duron.
- Disabled the serial console by default since it was slowing down testing.
- Added CPU detection for Pentium 4
- Minor bug fixes

Version 2.7 (12/Jul/2001)

- Expanded workaround for errors caused by BIOS USB keyboard support to include test #5.
- Re-worked L1 / L2 cache detection code to provide clearer reporting.
- Fixed an obvious bug in the computation of cache and memory speeds.
- Added a menu option to disable the serial console.
- Changed on-line menu to stay in the menu between option selections.
- Fixed bugs in the test restart and redraw code.
- Adjusted code size to fix compilation problems with RedHat 7.1.
- Misc updates to the documentation.

Version 2.6 (25/May/2001)

- Added workaround for errors caused by BIOS USB keyboard support.
- Fixed problems with reporting of 1 GHZ + processor speeds.
- Fixed Duron cache detection.
- Added screen buffer so that menus will work correctly from a serial console. (Code provided by Jani Averbach.)
- The MemTest86 image is now built in ELF format.

Version 2.5 (13/Dec/00)

- Enhanced CPU and cache detection to correctly identify Duron CPU and K6-III 1mb cache.
- Added code to report cache-able memory size.
- Added limited support for parity memory.
- Support was added to allow use of on-line commands from a serial port.
- Dropped option for changing refresh rates. This was not useful and did not work on newer motherboards.
- Improved fatal exception reporting to include a register and stack dump.
- The pass number is now displayed in the error report.
- Fixed a bug that crashed the test when selecting one of the extended tests.

Version 2.4

- The error report format was reworked for better clarity and now includes a decimal address in megabytes.
- A new memory move test was added (from Robert Redelmeier's CPU-Burn)
- The test sequence and iterations were modified.
- Fixed scrolling problems with the BadRAM patterns.
- Updated and improved CPU and cache detection.

Version 2.3

- Measurement and reporting of memory and cache performance was added.
- All of the test routines were rewritten in assembler to improve both error detection and speed.
- A progress meter was added to show pass and test completion.
- The screen layout was reworked to hopefully be more readable.
- Support for creating BadRAM patterns was added. (Code was provided by Rick van Rein.)
- An error summary option was added to the online commands.

Version 2.2

- Added two new address tests.
- Added an on-line command for setting test address range.
- Optimized test code for faster execution (-O3, -funroll-loops and -fomit-frame-pointer).
- Added and elapsed time counter.
- Adjusted menu options for better consistency.

Version 2.1

- Fixed a bug in the CPU detection that caused the test to hang or crash with some 486 and Cryrix CPU's
- Added CPU detection for Cyrix CPU's
- Extended and improved CPU detection for Intel and AMD CPU's
- Added a compile time option (BIOS_MEMSZ) for obtaining the last memory address from the BIOS. This should fix problems with memory sizing on certain motherboards. This option is not enabled by default. It may be enabled by default in a future release.

Version 2.0

- Added new Modulo-20 test algorithm.
- Added a 32 bit shifting pattern to the moving inversions algorithm.
- Created test sections to specify algorithm, pattern, cache and refresh rate.
- Improved test progress indicators.
- Created pop-up menus for configuration.
- Added menu for test selection.
- Added CPU and cache identification.
- Added a "bail out" feature to quit the current test when it does not fit the test selection parameters.
- Re-arranged the screen layout and colors.
- Created local include files for I/O and serial interface definitions rather than using the sometimes incompatible system include files.
- Broke up the "C" source code into four separate source modules.

Version 1.5

- Some additional changes were made to fix obscure memory sizing problems.
- The 4 bit wide data pattern was increased to 8 bits since 8 bit wide memory chips are becoming more common.
- A new test algorithm was added to improve detection of data pattern sensitive errors.

Version 1.4

- Changes to the memory sizing code to avoid problems with some motherboards where MemTest86 would find more memory than actually exists.
- Added support for a console serial port. (Thanks to Doug Sisk)
- On-line commands are now available for configuring MemTest86 on the fly (see On-line Commands).

Version 1.3

- Scrolling of memory errors is now provided. Previously, only one screen of error information was displayed.
- MemTest86 can now be booted from any disk via lilo.
- Detection of up to 4gb of memory has been fixed is now enabled by default. This capability was clearly broken in v1.2a and should work correctly now but has not been fully tested (4gb PC's are a bit rare).
- The maximum memory size supported by the motherboard is now being calculated correctly. In previous versions there were cases where not all of memory would be tested and the maximum memory size supported was incorrect.
- For some types of failures the good and bad values were reported to be same with an Xor value of 0. This has been fixed by retaining the data read from memory and not re-reading the bad data in the error reporting routine.
- APM (advanced power management) is now disabled by MemTest86. This keeps the screen from blanking while the test is running.
- Problems with enabling & disabling cache on some motherboards have been corrected.

What's New?

Version 11.1 (Build 1000) 31/Oct/2024

Version 11.0 (Build 1000) 13/Jun/2024

Version 10.7 (Build 1000) 8/Feb/2024

Version 10.6 (Build 3000) 11/Oct/2023

Version 10.6 (Build 2000) 29/Aug/2023

Version 10.6 (Build 1000) 17/Aug/2023

Version 10.5 (Build 1000) 19/June/2023

Version 10.4 (Build 1000) 20/April/2023

Version 10.3 (Build 1000) 24/March/2023

Version 10.2 (Build 1000) 23/Dec/2022

Version 10.1 (Build 1000) 16/Dec/2022

Version 10.0 (Build 1000) 30/Sep/2022

Version 9.4 (Build 1000) 24/Jan/2022

Version 9.3 (Build 1000) 6/Oct/2021

Version 9.2 (Build 2000) 30/Jul/2021

Version 9.2 (Build 1000) 23/Jul/2021

Version 9.1 (Build 1000) 21/May/2021

Version 9.0 (Build 2000) 24/Feb/2021

Version 9.0 (Build 1000) 10/Feb/2021

Version 8.4 8/May/2020

Version 8.3 22/Nov/2019

Version 8.2 3/Jun/2019

Version 8.1 4/Jan/2019

Version 8.0 7/Dec/2018

Version 7.5 (Build 1001) 21/Feb/2018

Version 7.5 5/Feb/2018

Version 7.4 26/July/2017

Version 7.3 27/Feb/2017

Version 7.2 13/Dec/2016

Version 7.1 5/Aug/2016

Version 7.0 20/July/2016

Version 6.3.0 27/Jan/2016

Version 6.2.0 8/Sept/2015

Version 6.1.0 5/June/2015

Version 6.0.0 13/Feb/2015

Version 5.1.0 16/May/2014

Version 5.0 release for UEFI 3/Dec/2013

Version 4.3.7 13/May/2014

Version 4.3.6 14/Nov/2013

Version 4.3.5 24/Oct/2013

Version 4.3.4 2/Oct/2013

Version 4.3.3 11/Sept/2013

Version 4.3.2 22/Aug/2013

Version 4.3.1 8/Aug/2013

Version 4.3.0 10/Jul/2013

Version 4.2.0 18/Mar/2013

Version 4.1.0 Jan/2013

Version 4.0 28/Mar/2011

Version 3.5 3/Jan/2009

Version 3.4 (2/Aug/2007)

Version 3.3 (12/Jan/2007)

Version 3.2 (11/Nov/2004)

Version 3.1a (11/Mar/2004)

Version 3.0 (22/May/2002) - Provided by Eric Biederman

Version 2.9 (29/Feb/2002)

Version 2.8 (18/Oct/2001)

Version 2.7 (12/Jul/2001)

Version 2.6 (25/May/2001)

Version 2.5 (13/Dec/00)

Version 2.4

Version 2.3

Version 2.2

Version 2.1

Version 2.0

Version 1.5

Version 1.4

Version 1.3